1. Field Of The Invention
The present invention pertains to antifuse design for use in user configurable integrated circuits and the like. More particularly, the present invention pertains to an antifuse having a reduced susceptibility to misalignment of the mask layers which are used to form its features during the semiconductor fabrication process.
2. The Prior Art
Antifuses generally consist of two conductive electrodes separated by one or more layers of insulating material. Antifuses may be fabricated using standard semiconductor processing techniques. The lower conductor is covered with an insulating material, typically a silicon dioxide layer, into which a window is etched in the region where it is desired to fabricate the antifuse. The antifuse dielectric is then formed in this window region and is covered by one or more conductive layers which will serve as the upper electrode.
The actual vertical conductive area of a programmed antifuse is relatively small. In order to maximize circuit performance, it is desirable to make the antifuse dielectric window area as small as possible to minimize the capacitance contributed to the circuit by the antifuses which are to remain unprogrammed in the finished circuit after programming.
The desire to minimize the area of the dielectric window is counterbalanced, however, by the inherent limitations in photolithographic alignment techniques. At some point, the dielectric window area may be made so small that etching techniques or mask misalignments commonly encountered and considered normal in the semiconductor fabrication process can result in the window being placed such that no antifuse will be formed where one is intended to be formed.
Current design techniques have only one antifuse cell window in each antifuse cell. This window must be large enough to guarantee that an antifuse can exist within the misalignment tolerances which are characteristic of the process used to fabricate the integrated circuit containing the antifuses. In order to accommodate the expected worst-case misalignment, certain design margins must be placed into the antifuse layout, resulting in an increase of the capacitance of an antifuse which will ultimately remain unprogrammed in the finished and programmed integrated circuit. Typical present designs utilize an antifuse area of approximately 0.72 .mu.m.sup.2, e.g., 1.2 .mu.m.times.0.6 .mu.m, with a 1.2 .mu.m technology.